Evaluation of Dynamic Branch Prediction Schemes in a MIPS Pipeline

Increasing exploitation of Instruction Level Parallelism has been the key to high-performance computing in the past few decades. One of the most critical roadblocks to this parallelism is the presence of branches. Branches (both conditional and un-conditional) redirect the stream of instructions resulting in dead cycles in the front-end of the pipeline. In super-pipelined and superscalar architectures, branch costs increase with the number of stages before branch resolution and the width of the pipeline respectively. In this project, we explore some well-known branch prediction schemes proposed in the literature that can alleviate this problem. We write benchmarks to observe the superiority of individual branch predictors in different situations. We find different patterns in a code that might take advantage of each of these predictors. We find that the bimodal (1level) 2-bit predictor performs best for most of the benchmarks. We also explore some of the hardware costs associated with these techniques.